Graphic controller with DDR2 and LVDS on EP4CE6

Hi Lorenzo,

"1) Is it possible to control one DDR2 x32 chip using 2 Top x8 groups and 2 Bottom x8 groups?"

• Yes but it's has a high latency

"2) My DDR2 run at 200 MHz, it is fair to say that it is enough to use 4 x8 groups and Soft Memory Controller, so can i use 4 x8 Bottom groups of a Cyclone V E A2 UBGA484 or FBGA484 or MBGA383?"

• Yes, it's depend on the data width.

"3) Apart from speed, are there any other parameters that differentiate Soft Memory Controller from Hard Memory Controller?"

• Usually the soft memory controller will use the soft logic instead of harden logic.
• I think you will need to have your own memory controller for the soft logic.

"4) Is there an example of an application of a DDR2 memory controller without the NIOS?"

• You can here: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?f:guidetm83741EA404664A899395C861EDA3D38B=%5BIntel%C2%AE%20Cyclone%C2%AE%3BCyclone%C2%AE%20V%20FPGAs%20and%20SoC%20FPGAs%5D&f:guidetm5203BAD641A146288EA061D522BFD990=%5BMemory%20Interfaces%20and%20Controllers%5D
• The example design with DDR2 memory IP may already EOL, thus the design may not available if you cannot find it in the design store.

Regards,

Adzim