Getting rid of some differential I/O pins and PowerPlay warnings

I am using two LVDS channels and every channel needs differential IOs so this is why I need the automatically generated negative signals. I was wondering if I could define them in the top module and then use a buffer as people do with other FPGAs by means of the ALT_INBUF_DIFF module (which does not work in MAX10 devices). So I should just ignore the warning and use the auto-generated signals as I implemented them in the Pin Planner Tool, right? That would do the trick but it would be nice if there was a proper way to define the differential inputs on the op module and buffer them to send them as one data signal to the LVDS megafunction (which only accepts a single signal, not differential).