Honored Contributor
Honored ContributorHi wombat,
I still face the issue. I will paste the output of get_service_paths below. Can you please take a look ? Here is the procedure I followed: 1. download bitstream (i use a time limted ethernet core)>download_sof ./DE4_Ethernet_time_limited.sof File ./DE4_Ethernet_time_limited.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details. Info (210040): SRAM Object File ./DE4_Ethernet_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00BD Info: ******************************************************************* Info: Running Quartus II 32-bit Programmer Info: Version 12.1 Build 177 11/07/2012 SJ Full Version Info: Copyright (C) 1991-2012 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, Altera MegaCore Function License Info: Agreement, or other applicable license agreement, including, Info: without limitation, that your use is for the sole purpose of Info: programming logic devices manufactured by Altera and sold by Info: Altera or its authorized distributors. Please refer to the Info: applicable agreement for further details. Info: Processing started: Sat Apr 13 05:33:46 2013 Info: Command: quartus_pgm --quiet -z -m JTAG -o p;./DE4_Ethernet_time_limited.sof Info (213045): Using programming cable "USB-Blaster [8-2]" Info (213011): Using programming file ./DE4_Ethernet_time_limited.sof with checksum 0x09B20EC8 for device EP4SGX230KF40 at 1 Info (209060): Started Programmer operation at Sat Apr 13 05:33:54 2013 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x024090DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Sat Apr 13 05:34:12 2013 Please enter i for info and q to quit: [I don't close this message] In a new tab, 2. open system console in command line mode
> system-console -cli
Apr 13, 2013 5:38:42 AM com.altera.systemconsole.internal.core.SystemConsole$PluginDiscovery run INFO: Finished initialization Apr 13, 2013 5:38:42 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering JTAG connections Apr 13, 2013 5:38:48 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering USB connections -------------------------------------------------------------------------------- Version 12.0 178 Copyright (C) 1991-2012 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information is expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreements, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Welcome to Altera's System Console This Tcl console provides access to the hardware modules instantiated in your FPGA. You can use System Console for all of the following purposes: * To start, stop, or step a Nios II processor * To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters * To sample the SOPC system clock as well as system reset signal * To run JTAG loopback tests to analyze board noise problems * To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes In addition, the directory <QuartusII Dir>/sopc_builder/system_console_macros contains Tcl files that provide miscellaneous utilities and examples of how to access the functionality provided. You can include those macros in your scripts by issuing Tcl source commands. -------------------------------------------------------------------------------- Apr 13, 2013 5:38:48 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Executing startup script /home/deepak/altera/12.0/quartus/sopc_builder/system_console_macros/system_console_rc.tcl % set mypath [ lindex [ get_service_paths master ] 0 ]
% set mypath [ lindex [ get_service_paths master ] 0 ]
% open_service master $mypath
path cannot be found
while executing
"open_service {master} {}"
while executing
"open_service master $mypath"
now, i observe a very strange behavior summarized below:
- My script to write into JTAG master is as follows: set jtag_master [lindex [get_service_paths master] 0];
open_service master $jtag_master; master_write_32 $jtag_master $reg_400 0x00000000; close_service master $jtag_master;
I download the bitstream and run the above script, it runs perfectly fine. Then I wait 10 minutes and run the same script again. This time, open_service master fails giving the folloiwing error: Path cannot be found while executing "open_service {master} {}" while executing "open_service master $jtag_master" To run the script again, I need to reboot the PC. Looks like the JTAG master times out after some time. Has this behavior been observed before ? Appreciate your thoughts. Update: I dont see any obvious STA timing errors in the design (from report). Also, I tried changint the DE4 boards to make sure that its not a hardware issue. I can confirm that I see this issue even if I change the board. Looks something is wrong in software settings. Any pointers ? Thanks Deepak
