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anm's avatar
anm
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

get_pins command not returning results

Hi, I am using Quartus Prime v19.1 Standard Edition. I can see in Quartus Timing Analyzer that I have an unconstrained clock, more specifically the following one: adbg_top:dbg_top|adbg_wb_module:i...
  • anm's avatar
    anm
    5 years ago

    After several tries I managed to "find" the Q pin of the register by using the "-compatibility_mode" option of the "get_pins" command. This is the one that helps traverse the hierarchies of modules, and the command I used was the following:

    get_pins -compatibility_mode dbg_top|i_dbg_wb|wb_biu_i|str_sync_wbff2|q

    where "str_sync_wbff2" is the name of the register and "q" is the output of the ff that acts as a clock.

    After that I was able to apply a constraint on it.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

You can also use -hier which is used to search all hierarchical levels of the timing netlist using wildcards. In general, though, using the GUI to find and target stuff like this will make your life much easier. If you're not familiar with it, in the Quartus Text editor, in a .sdc file, go to Edit->Insert Constraints and choose one. The browse buttons in those dialogs open the Name Finder which lets you easily search the netlist, including enabling the compatibility mode or hierarchical search options.

As far as your design is concerned, though, why do you want to false path something the tool is indicating as a clock (unless I'm reading your last post incorrectly and that once you were able to find the pin you put a clock constraint on it)?

#iwork4intel

  • anm's avatar
    anm
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi @sstrell​

    thank you very much for your reply, it is much appreciated.

    No your intuition is right, I am applying a "false_path" on it.

    This is the Bus Interface Unit of the "Advanced Debug Interface" (Opencores). As it is not my design, my initial thought was to keep it as is.

    As you can see in the attached file, there is a register "str_sync_wbff2" which Quartus complains about being a clock. This register is assigned to a wire "start_toggle" and this wire exists in the sensitivity list of an "always" block.

    So this is why the tool interprets it as a clock. Nevertheless, I think the intention of the designer was not for it to be accounted as a clock.

    As you can imagine there are clocked paths associated with this register since the "adbg_wb_biu" module operates with two "official" clocks:

    tck_i --> is the clock coming from the JTAG cable

    and

    wb_clk_i ---> is the clock of the Wishbone bus, generated by an Altera PLL.

    So my first idea was to false path all the paths from this generated clock (str_sync_wbff2), to all the paths of the other 2 clocks and see if get the intended behavior.

    I think that for FPGA designs it is a general advice to not over-constrain the design, so making it a "false_path" was the simplest I could do.

    This Debugger is part of a larger implementation, an OpenRISC processor, that I am trying to implement. So there are different designs combined together. This is my very first attempt.

    Always feel free to add your thoughts, I am happy to discuss.

    Kind regards,

    anm