Honored Contributor
Honored ContributorHi Nial,
I am experiencing a problem similar to yours and I am trying to figure out possibly the same solution need. In my case I need to generate a differential output clock signal (with 737 MHz) through a PLL. Appearently the problem is that Quartus doesn´t know that the pins I am using are even dedicated PLL clock outputs. For first I would try to verify, on the datasheet of your FPGA chip, if the pin you are using is just meant to be used as a normal I/O pin, or if that has optionally the function to read in a PLL clock. If this is not the case, then you may just identify which pins on your chip are dedicated to this usage, and then just use this one instead of the one you are currently using. This is at least what I was reading about PLL outputs, but it should work even the way around. I´ve got this informations on this note: http://www.altera.com/literature/hb/qts/qts_qii51006.pdf I suppose that it is possible to tell Quartus II to assign to your input signal a dedicated route for global clock signals. In my case now I have defined my signal as Global clock signal, hoping that the Fitter will assign a dedicated route to it, but what I see is that even if my signals are owning to the PLL_L2 on bank 1C of my Stratix IV, the PLL itself is allocated to PLL_L3 on bank 2C, which is maybe why the routing is not optimal, and I get limitations due to the jitter. I´m not an expert and still I am blocked with this concepts, but I hope this helps a little bit. Giovanni.
