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Altera_Forum's avatar
Altera_Forum
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15 years ago

Generic shift register

Hello,

I would like to create a shift register of multiple delay as depicted in the picture joined.

The following code is an example with 3 registers of 8 bits. 


library IEEE;
use IEEE.std_logic_1164.all;
entity ShiftRegister is
    port
    (
        clock : in  std_logic;
        reset : in  std_logic;
        x0    : in  std_logic_vector(7 downto 0);
        x3    : out std_logic_vector(7 downto 0)
    );
end ShiftRegister;
architecture arch_ShiftRegister of ShiftRegister is
signal x1 : std_logic_vector(7 downto 0);
signal x2 : std_logic_vector(7 downto 0);
begin
    process(reset, clock)
    begin
        if reset = '1' then
            x1 <= (others => '0');
            x2 <= (others => '0');
            x3 <= (others => '0');
        elsif rising_edge(clock) then
            x1 <= x0;
            x2 <= x1;
            x3 <= x2;
        end if;
    end process;
end architecture arch_ShiftRegister;
The problem is that in the real application, there will be about 50 registers, so I would like to avoid to copy 50 times the same lines (moreover I would like that the number of registers be configurable with a generic value).

I think this is possible with the for generate instruction, but I have never use it and I am not comfortable with it. I have looked for examples in books, but I still didn't get how to use it for what I want to do.

Does anybody can help and provide such code ?

Thanks in advance

Jérôme

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    No need for generate loop at all. just add a generic and use attributes: 

    
library IEEE;
use IEEE.std_logic_1164.all;
entity ShiftRegister is
    generic (
        N_REGS : integer
    );
    port
    (
        clock : in  std_logic;
        reset : in  std_logic;
        x0    : in  std_logic_vector(7 downto 0);
        x3    : out std_logic_vector(7 downto 0)
    );
end ShiftRegister;
architecture arch_ShiftRegister of ShiftRegister is
  type slv_array_t is array(0 to N_REGS-1) of std_logic_vector(x0'range);
  signal sr : slv_array_t;
  
begin
    process(reset, clock)
    begin
        if reset = '1' then
           sr <= (others => (others => '0'));
        elsif rising_edge(clock) then
           sr <= x0 & sr(0 to sr'high-1)
        end if;
    end process;
    x3 <= sr(sr'high);
end architecture arch_ShiftRegister;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi Tricky,

    I just browse the quartus template and find it also. I didn't get that it could be directly done using an array of vector.

    Thank you.