Generate programming file for multiple device chain (HDL and Nios code)

No you will have to put the two sof files one after the other, it is the only way both FPGAs will read their respective configurations. In this mechanism, the slave FPGA will attempt to read its image just after the master FPGA is finished reading its own, so if you put the elf file between the two images the second FPGA won't configure itself.

Then there is the problem of the Nios CPUs. The first FPGA is the only one capable of driving the EPCS in application mode. Besides the default bootloader embedded in the EPCS controller will jump over the first sof image and will try to read the software application there. In your case you will need to write a specific bootloader that will be able to jump over both images.

If you need a Nios in the second FPGA you will also need a specific bootloader, but you will still need to use the first FPGA to read into the EPCS so you will need to implement a means of communication between the two FPGAs.