general question regarding Signal TAP

1) You would use usually enable all signals for trigger, if any of them is a meaningful trigger candidate. Resource economy and timing constraints with critical design can be a reason to use only selected signals.

2) The acquisition clock would be the system clock in most cases. It should be synchronous to your design under test at least, may an integer multiple of the system clock, but most likely not above 100 or 200 MHz, because timing closure becomes rather difficult then.

Consider, that Quartus try to achieve timing closure for the SignalTap design part as it does for the rest of it. It it doesn't succeed, also failure of other design parts may occur. Timing violations show in SignalTap often as waveform artefacts.

Before Altera introduces the Storage Qualifier feature, it has been often necessary to us e a divided clock for long time-scale acquisitions, although it caused timing violations. Now, you can use divided clocks and similar as qualifier and keep all timing constraints.