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Hi vaka,
If I understand it correctly, you are trying to switch between specific data pattern and logic zero. If yes, then you could mux the parallel data input (mux between your data pattern and zero's) to your low latency PHY TX ie the tx_parallel_data. You would not need the tx_forceelecidle since you are still transmitting valid data (logic zeros is considered valid data as well). It is recommended for you to try your design with Modelsim simulation as well to verify the functionality before testing on hardware.
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Yes, that is exactly what I want to do. I think a single AND gate solves the problem easily however, I am using qsys and I don't know how to add an AND gate to qsys. I tried exporting the pattern to the top level, performing AND operation and importing the result as an input to the qsys system, but that does not work. I tried creating qsys component too, but that didn't go well either. Is there a way that I can implement AND operation inside qsys, so that I can give the signal for gating as an input to the system?
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