Gated transceiver operation on Transceiver SI Development Kit Stratix V GX board

Hi vaka,

If I understand it correctly, you are trying to switch between specific data pattern and logic zero. If yes, then you could mux the parallel data input (mux between your data pattern and zero's) to your low latency PHY TX ie the tx_parallel_data. You would not need the tx_forceelecidle since you are still transmitting valid data (logic zeros is considered valid data as well). It is recommended for you to try your design with Modelsim simulation as well to verify the functionality before testing on hardware.