Gated transceiver operation on Transceiver SI Development Kit Stratix V GX board

So, I have tried to use the Custom PHY, however I get some weird data at the output. Attached is the eye diagram. The line is overlapping with the eye diagram as a result of the fact that the bit clock and the signal that puts the transceiver in idle state are not locked, so they appear overlapped. However, I would have expected that that line coincides with the low level ('0'). I don't know if it matters that I terminate one of the differential outputs and use it as a single-ended to connect it to equipment...Also, could you tell me what exactly does the tx_forceelecidle do? I have read that the transceiver buffer is put in an idle state, but does that mean exactly? Is there no data transmission at all, are '0' sent or what...?