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Honored Contributor

13 years ago

Gated dedicated clock outputs

I'm currently not understanding an issue that turns up with my Stratix III EP3SL50 Device. what i try to do: In a PLL (altpll) I generate a 70 MHz clock from a 50 MHz clock. The resultin...

Altera_Forum

Honored Contributor

13 years ago

If that is the case, then I would suggest filing a Service Request with Altera.

Forum Discussion

Gated dedicated clock outputs

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