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Honored Contributor
Honored ContributorGated dedicated clock outputs
I'm currently not understanding an issue that turns up with my Stratix III EP3SL50 Device. what i try to do: In a PLL (altpll) I generate a 70 MHz clock from a 50 MHz clock. The resultin...
Altera_ForumHonored Contributor
Honored ContributorActually i am using a dedicated pll output pin of the PLL 1 block. I am aware that CLK0 ton CLK3 pins feeds the pll1 block. And i already use the derive clock uncertancy in a sdc file. I tried all combination of clk input and pll outputs but the problem always arrises. I really don t understand how to do it right, and i have had this problem with several designs for a long time
