Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Gated dedicated clock outputs

I'm currently not understanding an issue that turns up with my Stratix III EP3SL50 Device. what i try to do: In a PLL (altpll) I generate a 70 MHz clock from a 50 MHz clock. The resultin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

I am having the same problem:

Warning: PLL "PLL167MHz:PLL167MHz_Instance|altpll:altpll_component|PLL167MHz_altpll:auto_generated|pll1" output port clk[0] feeds output pin "SRAM1_clk_o~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

I tried to change the location of the feeding clock of the PLL (I am currently designing the board, so feeding clock ports are not placed yet), but I always have this warning, I also tried to change the PLL assignment...

But whatever I do, I have the same warning...

I've also read the application notes and the Cyclone III handbook, and when I do what is recomended, the warning still shows himself

How to fix this warning??