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Altera_Forum
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13 years ago

Gated dedicated clock outputs

I'm currently not understanding an issue that turns up with my Stratix III EP3SL50 Device. what i try to do: In a PLL (altpll) I generate a 70 MHz clock from a 50 MHz clock. The resultin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

It aligns the clock with the output data in case of a source synchronous output bus. In a source synchronous output it would be disadvantageous to have the output clock come from the dedicated PLL output pins as the timing (over the PVT range) is quite different.