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Altera_Forum
Honored Contributor
Honored ContributorGated dedicated clock outputs
I'm currently not understanding an issue that turns up with my Stratix III EP3SL50 Device. what i try to do: In a PLL (altpll) I generate a 70 MHz clock from a 50 MHz clock. The resultin...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you drive the clock out using a altddio_out component, the warning will go away. --- Quote End --- Yep, this works perfectly concerning the warning, It's gone! I connected _l / _h data inputs to 0/1 and with that propageted the clock to the output. Thanks for the hint. Compared to the previous version I now have additionally the DDIOOUTCELL_X25_Y51_N98 instance in my path, which is located at the pad, adding somewhat more than 1 ns to the time budget (which actually is not important). However the following point arises: Do I get something (besides the mere satisfaction of the fitter warnings), is it just the same or does it cost me something (if yes, what)?
