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As for the Warning, you get that because you are gating the clock and not going directly to a dedicated clock output. Use derive_clock_uncertainty to set the uncertainty representing the jitter produced.
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Actually, the 70 MHz output is input to an image sensor array, from where I have a source synchronous I/F (data nand clock) back to the FPGA. So the output timing is not so important. Up to now, I used ordinary data pins for the clock outputs, but in a redesign I intend to use dedicated clock outputs as I have them available now due to design changes.
My understanding was to use the altclkctrl as a (gated) driver to a regional (upper left quarter) clock net which then directly drives the dedicated clock outputs (of bank 8C).
The same construct (on another PLL output but with gating buffer, too) works perfectly with clocks used internally. I'm not worried about the jitter, but about not using an internal regional clock net.
May the increased jitter be systematic? (leading to asymmetric clock output duty clycles like 40/60 or someting like that)
Would it be preferrable to directly gate the clock output? (gating takes place during reset sensor only, so a non-perfect gating might be acceptable)
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