Gated dedicated clock outputs

If you are using the output clock(s) as the external clock for a source synchronous output interface from the FPGA, then yes you will need to create a clock on the output port with the -source being the output pin from the PLL. This clock then becomes the target of the -clock option on your set_output_delay constraints for the source synchronous output interface. If you aren't using that clock to constrain anything to/from the FPGA, then you won't need to create a generated clock on the output port.

As for the Warning, you get that because you are gating the clock and not going directly to a dedicated clock output. Use derive_clock_uncertainty to set the uncertainty representing the jitter produced.