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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
Altera_Forum's avatar
Altera_Forum
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15 years ago

FPGAs can work with non 50%/50% clocks.

And the PLLs can generate such clocks as well.

However, I can't tell you how small can the pulse be.

You'll have to try and design something and see how low you can go.