Gate level simulation of clock-less design

It's a pure simulator problem, but you probably need to change the design style to allow an initialization. As another option, adding a reset signal to the chain (by a NAND or NOR gate in place of an inverter) doesn't change the LE delay.

I wonder which insights you expect from this trivial simulation setup? The "design" will work in real hardware as a ring oscillator, but the frequency is too high (about 1 GHz with Cyclone families, even more with faster series) to generate an output signal within the I/O standard specifications.