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Altera_Forum's avatar
Altera_Forum
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10 years ago

gate level simulation error

Hi all, i have a problem in gate level simulation. actually i have two kits 1- cyclone IV gx EP4CGX150DF31C7 kit 2- SDALTEVK (ti) sdi kit. both kits can be connected through HSMC, duri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Add an "IO_MAXIMUM_TOGGLE_RATE" attribute, to each of the non-differential signals listed, and set it to "0 MHz". You can do this through the Pin Planner (enter "0" [zero] in the 'Toggle Rate' column for the relevant signal) or directly in the .qsf. You should end up with a .qsf entry, for each signal, similar to:

set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to genlock_no_ref

Looking at the names of all your culprit signals, this attribute looks to be valid.

Cheers,

Alex