functional simulation + STA = gate level simulation?

I usually also go directly from RTL to FPGA testing, when TimeQuest gives the green flag.

That said, there are a few caveats to keep in mind.

- You may have gotten your constraints wrong.

- There may be subtle inconsistenties between what you describe in HDL and what the synthesis tool produces.

Consider this trivial piece of VHDL when x is 'X'

y <= '1' when x = '1' else '0';

In RTL simulation, y will become '0'; post synthesis, y will become 'X'.

I don't recall ever coming across trouble with this when designing for FPGAs, only for ASICs. Best beware.

- There may be bugs/limitations in the synthesis tools and STA tools.

Ie, once upon a time in an old design, TimeQuest was missing a timing failure in totally normal register to register transfer in the same clock. But the bug showed up in gate level simulation (and in the FPGA).

PS: I have a very degree of confidence in TimeQuest. Don't want to start any flame war but I would not extend the same degree of confidence to lesser STA tools such as Altera's Classical Timing Analyzer or Xilinx's TRACE.