functional equivalence with blif generation

Hello,

I recently tried to generate .blif files from quartus's TcL console.

The circuit was a plain register with an asynchronous reset line.

The problem is that the blif-dumper responds with a message that the blif file is not functionally equivalent to the original verilog circuit

My question is: How does quartus check for functional equivalence between a blif and the verilog code?