Full adder vhdl

Hi, I am very new to VHDL and I am struggling with errors.

I am trying to design a FULLADDER and to use it to design a Wallace Tree technique.

My first question is do anyone know how to combine, to use full adder to get a wallace Tree?

In the code below I've started to design a full adder, but I've an error : Error (10500): VHDL syntax error at test.vhd(23) near text "signal"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

Library ieee; --import library

use ieee.std_logic_1164.all;

package WTree is

component FullAdder

port(

in1,in2,in3: in std_logic;

o1,o2: out std_logic);

end component;

end package;

Library ieee; --import library

use ieee.std_logic_1164.all;

Library work; --import library

use work.WTree.all;

entity test is

port(

in1,in2,in3: in std_logic;

o1,o2: out std_logic);

end entity;

signal D1,CO1: std_logic;

architecture WallaceT of test is

--For U1: FullAdder use entity work.test(WallaceT);

begin

U1: FullAdder port map(in1,in2,in3,o1=>D1,o2=>CO1);

o1 <= in1 xor in2 xor in3;

o2 <= (in1 and in2) or (in2 and in3) or (in3 and in1);

end architecture;

Thank You in advance