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Altera_Forum
Honored Contributor
10 years agoFT2232H in Sync FIFO Mode - TXE# stuck high
hi,
I have a Moprh-IC-II board and I'm trying to communicate via USB with a FT2232H in Sync FIFO Mode and D2XX Drivers. I manage to have the 60MHz clock input (my main fpga clock) from the ft2232h, and i can transfer data from the PC to my fpga via ft2232h with FT_Write(). FIFO Mode seems to work as expected on this side. The RXF# signal is working, going low when needed (I'm checking signals with SignalTap). But I can't send data from my fpga to the pc, the TXE# signal (active low) is stuck high and I can't find how to have it low to be able to receive data... If you have any idea on what my issue could come from ? Tank you, Alexis17 Replies
- Altera_Forum
Honored Contributor
I've not worked with the hardware in some time, so I couldn't say exactly when TXE# goes low.
- Altera_Forum
Honored Contributor
Hi,
--- Quote Start --- Here's some of the code I used to configure channel A for sync fifo mode. Maybe something will stand out. UCHAR Mask_A = 0xff; // all outputs UCHAR Mode_A = 0x40; // high speed synchronous fifo UCHAR Reset_Mode = 0x00; UCHAR LatencyTimer = 2; // connect with Channel A and set Mode ftStatus = FT_Open(device_number_a, &FTDIHandle_A); FT_SetBitMode(FTDIHandle_A, 0xff,Reset_Mode); Delay(.01); FT_SetBitMode(FTDIHandle_A, Mask_A,Mode_A); FT_SetLatencyTimer(FTDIHandle_A, LatencyTimer); FT_SetUSBParameters(FTDIHandle_A,65536,65536); FT_SetFlowControl(FTDIHandle_A,FT_FLOW_RTS_CTS,0x00,0x00); FT_SetTimeouts(FTDIHandle_A, 5000, 5000); --- Quote End --- TXE# should obviously be low after this kind of settings or am I missing / misunderstanding something ? Alexis. - Altera_Forum
Honored Contributor
Hi,
SOLVED : I'm not using the "USB Remote WakeUp" mode, and the master I had taken from the FTDI project of AN_165 was completely ignoring the pin SIWU. At first sight, it seemed quite ok and I didn't question it. BUT, when unused, the SIWU pin has to receive '1'... PS: is it possible to mark a thread as Solved in alteraforum? I'd like to THANK YOU gj_leeson for everything you've done to help me! Alexis. - Altera_Forum
Honored Contributor
I'm glad you solved your problem. I didn't even think about the SIWU pin as I've always tied it HI.
- Altera_Forum
Honored Contributor
Hi,
Do you know the datarate you've reached with this setup ? I've reached 32MBytes/s this far, but the size of buffers or the data latency timer don't seem to change anything on my datarate. Alexis. - Altera_Forum
Honored Contributor
For big transfer buffer size and data latency doesn't affect speed.
For small transfer I set latency to 1 ms and use SIWO. Key to improve performance is to make less bigger Write call to use less USB microframe. I reached 50 MB/S in read and 14 MB/S in read (see last image into http://electro-logic.blogspot.it/2014/02/fpga-comunicazione-ad-alta-velocita_16.html) - Altera_Forum
Honored Contributor
Thank you for your feedback.
Is it normal not to receive those "2 status bytes" that I've read about in many datasheets about usb transfer ? Alexis;