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Altera_Forum's avatar
Altera_Forum
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15 years ago

FSM Problem!

Hi,

I’m using the Case statement inside process that driven by the system clock (“present state” only (no “next state”)). Inside the case I’m using several counters. In Modelsim simulation, the code works well but when I’m burning the code in my CPLD, the code not acting as it should (according to state machine).

What could be the problem? I need help…

Thanks, Idan

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It's hard to figure out this certain thing.

    It's good if you can share the code.

    And let's see what we can help!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The difference between simulation and real life is that in real life the input signals into your CPLD can be 'very' asynchronous. As a result the registers which make up your state machine may see different values for the changing input and may/will transition into an undefined state or incorrect state. So it is important that you synchronize all external asynchronous inputs (using the recommended 2 register synchroniser)