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Altera_Forum's avatar
Altera_Forum
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17 years ago

FSM design/reset

Hi! I'm currently implementing some control logic using an FSM on a Stratix II chip. I'm having issues writing a "clean" FSM design, as I don't have an external reset signal available. My questions a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

But shouldn't I then be able to manually encode the FSM's reset state to all zeros so that it would come up in that state after powerup using the attributes you mentioned (I guess this somehow has to do with the safe state machine "feature", but I don't see why this approach would not work). Or is it just "cleaner" to generate the reset and then use it for the FSM?

Have a good start to the new week!

Moritz