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Altera_Forum's avatar
Altera_Forum
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17 years ago

FSM design/reset

Hi! I'm currently implementing some control logic using an FSM on a Stratix II chip. I'm having issues writing a "clean" FSM design, as I don't have an external reset signal available. My questions a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

It works and I have used it for several designs. Counter is not strictly a state machine from the compiler prespective, it is based on adder(unlike old style counters which were based on state machine design). The tools guarantee that registers power up low(except those with preset) provided power-up don't care is off in the compiler settings.