FSM design/reset

Hi,

You can generate internal reset for whatever purpose after power up or any time by using basic logic or a small counter.

signal count : unsigned(3 downto 0);

-- to prevent compiler optimising away count

attribute keep_count:boolean;

attribute keep_count of count :signal is true;

process

begin

wait until clk = '1';

if count < 15 then

count <= count + 1;

end if;

if count < 10 then

reset <= '1';

else

reset <= '0';

end if;

end process;

edit:

To be on safe side you may also add keep attribute to reset, also make sure that the (power-up don't care) is off so that the count starts at 0 always.