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Altera_Forum
Honored Contributor
Honored Contributorfsm debuging
fsm debugging
Hi I started to check the fsm on real time and got some strange behaviors. I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get how to work with him. So I went to ModelSim and created a test bench and got the next wave form There is a lot of signals there but I can see that the logic is working, the only problem is that the pwm is not working (the signal in red) and I don't know why. This design works when all the code is in the same file (without components) I had the same thing with the encoder enable nut I succeeded in solving it by giving him a default value of '0'. for another way to look were the program got stuck I used a 7 seg display where at the commands bk,fd - 1,2 the fsm got stuck at state 15 and in the commands rt,lt - 3,4 the fsm got stuck at state 1033 Replies
Altera_Forumwell I still don't understand why it's not working so...
back to a more simple fsm with only on problematic component that is Motion_Pwm and still getting the same annuoing problem with the pwm signal any ideas why?- Altera_Forum
I have changed all of pwm signals in the lowest of the heirarchy and the compiler doesn't seem to mind.
maybe I need to replace the compiler with a tougher one (; I don't know if it will help but I have put a flag in the pwm component and the signal doesn't change - Altera_Forum
then the problem is probably two things tring to drive that signal inside whatever component. Go into the component and change the port it is connected to to std_ulogic. Keep following this up the heirarchy.
- Altera_Forum
just to change the port declartion to std_ulogic...
the compiler hasn't gave any warnings - Altera_Forum
it wont be components, it will be a code error.
The best way to find it - declare m_p_pwm as a std_ulogic instead of std_logic. std_ulogics are only allowed 1 driver, so the compiler will tell you which two processes are driving it. - Altera_Forum
thanks
I know that but I just can't find it... and I didn't had that problem when every thing was in one file... I am sure the problem is form the components in some way - Altera_Forum
'X' means you have two sources driving 1 signal.
- Altera_Forum
Hi Tricky
I have added a flag and some states in order to isolate the problem in addition to the 3 ff reg I have added ... this is the result. as you could see the M_P_pwm signal is still in the unknown state 'x' I added some images that maybe helpfull - Altera_Forum
pwm component port map
motion_pwm_comp:Motion_Pwm generic map ( DC => 17 ms, clock_period => 20 ms, max_pulse => 1 ms, min_pulse => 2 ms, neutral_pulse => 1.5 ms ) port map ( Rst => System_N_Reset, Clk => System_Clk_50MHz, Enable => M_P_En, Pwm => S_M_P_Pwm, pulse_length => S_FSM_M_P_pulse_length ); - Altera_Forum--- Quote Start --- you can always output a "ready" or "valid" signal from your state machine to enable other reigsters. --- Quote End --- like so when I use the enable like a valid flag --- Quote Start --- S_Pwm_valid_reg: process (System_Clk_50MHz,System_N_Reset) begin if (System_N_Reset = bit_low) then M_P_PWM <= bit_low; elsif rising_edge (System_Clk_50MHz) then if (M_P_en = bit_high) M_P_PWM <= S_M_P_PWM else M_P_PWM <= bit_low; end if; end process S_Pwm_valid_reg; --- Quote End ---
