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I will be glad if anybody can tell me if this classification is indeed useful in today's sequential design.
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Unfortunately I can't, I basically share your point of view in this regard. Determining the maximum speed of a FSM block is almost meaningless without considering the adjacent logic, where are the input signals originated from and what's the output's target? If you refer to the Altera FSM templates, the mealy design is involving more complex logic for the output signals and thus can be expected slower.
Some additional remarks related to the basic Mealy/Moore designs as presented in Altera design templates:
- They only work correctly, if the input signals have been already synchronized to the clock respectively are originated from the same clock domain
- The output signals have glitches, if they are used as direct output signals without additional registers
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