FSM coding.

With my full respect to Moore & Mealy for their efforts, I have worked over a decade in FPGA design and never needed to to categorise FSM as such.

I design FSM as the logic requires and it may end up with outputs depending on either state only(call it Moore) or state and input(call it Mealy) i.e. probably a mixed Moore Mealy with different proportions...

I will be glad if anybody can tell me if this classification is indeed useful in today's sequential design.

With regard to timing performance, I believe it is more to do with the design itself than being Moore or Mealy since both need be pipelined correctly.