FSM Caught in impossible State

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--HPI_FPGA mode state machine combo
HPI_FPGA_mode_fsm : process(clk_ddr, reset_n) begin
    if(reset_n = '0')then
              current_HPI_FPGA_state <= HPI_FPGA_idle;
                
    elsif(clk_ddr'event and clk_ddr = '1')then
        current_HPI_FPGA_state <= next_HPI_FPGA_state;
       
        case current_HPI_FPGA_state is
.
.
.
           when HPI_FPGA_wait_read_mult_done =>
              if (mult_done_sig = '1') then
                    next_HPI_FPGA_state <= HPI_FPGA_write_to_usb;
              else 
                   next_HPI_FPGA_state <= HPI_FPGA_wait_read_mult_done;
              end if;
.
.
          end case;
       end if;
  end process; 

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It would have been clearer if we could see the exact (complete) code, instead of an excerpt.

As it looks here, you have a current_state and a next_state, but both are inside a clocked process, which delays the actual assignment by one clock, and that can't be good. You have to either export the 'case/endcase' code to a separate combinatorial process (which I prefer (I will catch some flak for saying this)) or directly assign current_state in the transitions.

Regards,

Josy