Hi, I'am so sorry if there are some mistakes in english. I try to modify the frequency of StratixIV (used the PLL in SOPC builder), always, i obtained with the clock tools the same frequency 100Mhz. I see that's abnormal problem. Any suggestion please :(.

Hello Aflouton, Can you post your timing constraints file?(*.sdc file) Does it have the following lines in it: derive_pll_clocks -create_base_clocks? Have you regenerated the SOPC project after you have modified the PLL? Have you recompiled the project after you have modified the PLL in SOPC builder? Thanks, Ben

Hello Protocol Engineer, Think you very much for your reply. Of course in regenerated my SOPC in every change. Also the project. in the pll.sdc there are the two line "derive_pll_clocks -create_base_clocks" but this line is comment. This is the file pll.sdc # Uncommenting one of the following derive_pll_clocks lines# will instruct the TimeQuest Timing Analyzer to automatically# create derived clocks for all PLL outputs for all PLLs in a# Quartus design. # If the PLL inputs are constrained elsewhere, uncomment the# next line to automatically constrain all PLL output clocks.# derive_pll_clocks # If the PLL inputs are not constrained elsewhere, uncomment# the next line to automatically constrain all PLL input and# output clocks.# derive_pll_clocks -create_base_clocks Thanks for your helps

Hello Aflouton, Do you have any other sdc files that you are using in your project? If not, without including timing constraints in your project, you won't get correct timing analysis. You might try uncommenting the derive_pll_clocks line mentioned before in the pll.sdc file, which will derive the timing constraints from the pll in your SOPC project. You will also need to make sure the sdc file is included in your project(in Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file). -Ben

Hello Protocol Enginner, Yes i have other sdc file "CPU.sdc, pll.sdc, and tse_mac_constraints.sdc". There are two line contain derive_pll_clocks. wich line i uncommentig. When i try to go in timeQuest under assignement setting i find two file CPU.sdc and tse_mac_constraints.sdc , and the pll.sdc not included. Thanks friend,

Uncomment the line "derive_pll_clocks -create_base_clocks" in pll.sdc and add in pll.sdc to your project through Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file. Let me know how this works.

Frequency of StratixIV | Altera Community

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Altera_Forum
Honored Contributor
14 years ago
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NO I meant in the RTL viewer. What you are seeing is only the top level view. To find the pll you will need to go down the hierarchy by looking inside the SOPC component. You can also try to find it in the tree (tree list on the left of the rtl view).
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Ah ok; think you very much Daixiwen.:)
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Uncomment the line "derive_pll_clocks -create_base_clocks" in pll.sdc and add in pll.sdc to your project through Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file. Let me know how this works.

--- Quote End ---

Hi protocol Enginner,

Finally it work, i bought license. And i try to calculate the time with alt_timestamp() function:).

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Frequency of StratixIV

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