Frequency divider

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What I have done is to make a 7 bit counter and a 3 bit counter so four 7 bit counters and one 3 bit counter connected in series gives me delay of a little more than 10ms.

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This would be a solution for breadboard circuit with TTL or CMOS counter ICs to achieve a minimum part count. With programmable logic, it's appropriate to build a single synchronous counter. You can generate a counter to 10000 with the MegaWizard or write a few lines of HDL code. The Quartus Editor has VHDL and Verilog design templates for counters, you can easily change it to a 10000 counter.

In situations, where a divided clock is necessary, use a clock enable rather than a divided clock. The first counter generates a overflow/carry signal, that is active for one period of the input clock. The cascaded counter gets the same input clock (=system clock) and the overflow as a clock enable. This way, you can cascade counters synchronously without timing issues.