Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFrequency Divider Timing Req. Never Met
I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- As said, I don't see a problem with the clock divider itself. clkout is a copy of a registered signal and in so far keeping the requirements for a clock divider. I assume the problem with clock enable is, that you don't want to change the subcircuit code. Otherwise there should be no problem to implement it. Normally, Quartus will be able to adjust the clock path for the delay caused by a frequency divider, if a domain crossing is involved. --- Quote End --- I see thank you for your opinions. But I have one more thing that tamper my mind. I have another clock that I use for other parts of my design. Is it possible for Timequest to fail analyzing them simultaneously? Because design works in practice.
