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As said, I don't see a problem with the clock divider itself. clkout is a copy of a registered signal and in so far keeping the requirements for a clock divider.
I assume the problem with clock enable is, that you don't want to change the subcircuit code. Otherwise there should be no problem to implement it.
Normally, Quartus will be able to adjust the clock path for the delay caused by a frequency divider, if a domain crossing is involved.
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I see thank you for your opinions. But I have one more thing that tamper my mind. I have another clock that I use for other parts of my design. Is it possible for Timequest to fail analyzing them simultaneously? Because design works in practice.
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