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Altera_Forum
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14 years ago

Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_Forum's avatar
Altera_Forum
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14 years ago

As said, I don't see a problem with the clock divider itself. clkout is a copy of a registered signal and in so far keeping the requirements for a clock divider.

I assume the problem with clock enable is, that you don't want to change the subcircuit code. Otherwise there should be no problem to implement it.

Normally, Quartus will be able to adjust the clock path for the delay caused by a frequency divider, if a domain crossing is involved.