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You didn't tell about the purpose of the divided clock in your design. Isn't it possible to use clkout as a clock enable instead of an actual clock? If I understand right, it's already active for one clkin cycle, as required for a clock enable in the clkin domain.
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I am using this divided clock to obtain low frequencies (such as 0.5 Hz) that I need in my design. This low frequency clock signal must drive a subcircuit that changes its output according to this divided clock. If I use this divided clock as clock enable then this subcircuit's output will change not in the frequency of divided clock but its actual clock during enable cycle.
My concern is about my VHDL code especially the cnt0 signal (where timing errors focused). Is it a wrong way to obtain this divided clock? Is there any other way to obtain a divided clock without timing errors?
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