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Honored Contributor
Honored ContributorFrequency Divider Timing Req. Never Met
I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Do you see the timing violation inside the clock divider? I would rather expect it in domain crossing assignment from clkin to clkout. If so, it won't show a problem of the clock divider itself rather than of how to use divided clocks in a design. --- Quote End --- Actually the design works as expected but I get lots of annoying warnings related to timing requirements and negative slacks.
