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Why doesn't it fail? When you launch TimeQuest and right click on the failing domain and do report_timing with detail set to full_path, what does it look like? What's the setup relationship?
You're clock rate is probably already really slow. This circuit should run really fast. So it should work, but something in the constraints, layout, etc. is not correct. You need to debug the timing report since it gives all of that information.
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When I do that all of the paths connected to cnt0(5) fails. Those paths have negative setup slacks with minimum pulse width violations.
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