--- Quote Start ---
A simple
and won't do. You have to
and the output flag of the source with the
and of the the output flags from the sinks before feeding the input flags of the sinks.
ready_source <= ready_sink0 and ready_sink1 ;
valid_sink0 <= valid_source and ready_source ;
valid_sink1 <= valid_source and ready_source ;
This will stall the source until both sinks are ready to accept a transfer.
--- Quote End ---
It's possible to use the "color plane sequencer" inorder to splitt up a single input stream into two separate output streams.
--- Quote Start ---
You can add a clock-domain-xing fifo (= dcfifo) on one of the outputs of your custom splitter and thus run the 2 chains at their original frequency. It seems that the 40 MHz chain is the one where you could best place the dcfifo. Although I thought I read somewhere that SOPC inserts rate converters (Timing Adaptor) automatically -> page 3.3 of the Quartus Handbook says:
--- Quote End ---
When adding an dc_fifo at the dout1 of the "color plane sequencer" I encountered some compatibility issues between the avalon-st interface and the avalon-st video interface. It seems that the avalon-st video interface doesnt support the "empty" signal and also the ready latency was different for the dc_fifo and the "color plane sequencer.
In order to solve the "empty" signal issue an "data format adapter" was placed before and after the dc_fifo.
To solve the latency issue an "timing adapter" was placed before and after the dc_fifo.
Honored Contributor
