Frame buffer IP

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Originally Posted by Daixiwen

I think you'll have to make a custom component for that, with one sink and two sources. Just connect all the signals from the sink to both sources, and for the 'ready' signal, do an 'and' between the signals from the two sources and put the result on the sink. I think it should work.

Depending on what you connect your component to, you may need to put some FIFOs to handle the cases when your two IPs aren't ready at the same time.

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A simple and won't do. You have to and the output flag of the source with the and of the the output flags from the sinks before feeding the input flags of the sinks.

ready_source <= ready_sink0 and ready_sink1 ;
valid_sink0 <= valid_source and ready_source ;
valid_sink1 <= valid_source and ready_source ;

This will stall the source until both sinks are ready to accept a transfer.

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I'm guessing that you'll have to run everything at 40Mhz when doing the VGA output. You need a higher pixel clock than with the NTSC output.

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You can add a clock-domain-xing fifo (= dcfifo) on one of the outputs of your custom splitter and thus run the 2 chains at their original frequency. It seems that the 40 MHz chain is the one where you could best place the dcfifo. Although I thought I read somewhere that SOPC inserts rate converters (Timing Adaptor) automatically -> page 3.3 of the Quartus Handbook says:

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The insert avalon-st adapters command on the System menu attempts to correct these errors automatically, if possible, by inserting the appropriate adapter types.

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