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hi,
In my SOPC design, I tryed connecting the Deinterlacer "dout" stream source to the Splitter's stream sink, but I get an error message saying: "The sink has a empty signal of 1 bits, but the source does not." So it looks like that since the Splitter core uses the "empty" signal the connecting cores also need to provide the "empty" signal.
Why aren't these cores setup so that they can be connected in SOPC and then ready to go? Must I provide an additional stage before the Splitter sink input and after it's source output inorder to provide the "empty" signal ?
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I'm not an expert in SOPC nor ST designs, as I had developed my own streaming interconnection, which I rather call dataflow interconnection, before looking into Altera's solution. However I looked up the ST- pin connections:
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empty : Width 0–8 : Direction Source → Sink : Optional : Indicates the number of symbols that are empty during cycles that contain the end of a packet. The empty signal is not used on interfaces where there is one symbol per beat. If endofpacket is not asserted, this signal is not interpreted.
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It looks to me that you have instantiated the de-interlacer with a 0 width for the empty signal, and so you must instantiate the splitter wit a 0-width empty signal as well.
Honored Contributor
