Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Frame buffer IP

We use 2 frame buffer IPs in our design. 1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have a similar situation in which I just want to use a simple SOPC Builder design to frame sync 4:2:2 YCbCr (720p) video in the un-referenced 74.25MHz clk domain... to black burst sync'd 74.25MHz clock domain by using the Clocked Video Input -> Frame Buffer (with DDR2 intf.) -> Clocked Video Output

But even though I uncheck the "video in and out use the same clock" option on the CVI and CVO general parameters options I still get an error message from SOPC builder (Quartus II v10.0) if I try to use a different dout-to-din (or din-to-dout) on the interface between the Frame Buffer and the Clocked Video blocks.

So then what is the purpose of the "video in and out use the same clock" parameter? What is the simplest way to solve my problem of differing frame rate read and/or write using the Video and Image Processing Suite blocks?