ESama
New Contributor
New Contributorfractional pll
Hello
I use a fractional pll in a cyclone 10 GX (10CX105YF672E5G) in order to generate a 100.000001 MHz from a 500 MHz.
Every thing is working well when the 500 MHz input frequency is present before the fpga is powered on but the fpll doesn't lock if the input frequency is provided after the fpga has been powered.
But in practice, I m not able to provide the input frequency at startup.
My question is: how could I lock the fpll in that case?
Very best regards
Etienne
