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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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This sounds like a video application to me, genlocking to a 50Hz source. I've used a Cypress CS2100/2300 for this in the past.

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Yes, gj_leeson. I am using the 2300 version of that series. Great chip. I'm using it for master clock MCLK to codec 24bit 48KHz.