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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_Forum's avatar
Altera_Forum
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8 years ago

If you use a normal oscillator you could for example count the number of clock cycles during one full period on the 50Hz signal. Then you can use software to compensate any timing measurement/synchronization you do, based on that clock cycles count.

But it really depends on your application and how accurate you need to be. If you really need those 10^6 cycles then I think your only solution is to use an external pll.