FPP Config of Arria II with Cyclone III

The FPGA configuration from connected parallel flash is performed by FPGA dedicated hardware rather than the PFL core. But you should be basically able to design a custom PFL version, that configures additional external FPGAs, by re-using the respective parts from the MAX II PFL design. The function could be completely separated from the PFL flash update operation, the latter even doesn't need to reside in your final design.