Honored Contributor
Honored Contributor@ted:
Okay, so instead of one 10Ge cable on each camera, you propose two CXP-6 connectors and cables (which could be bundled together and look like one cable)? That would transmit about 20% more data than 10Ge, which is good. Looks like the required cable (Gepco VHD1100) costs about $1/ft == $3.30/meter which is a bit high, but not out of the question. Of course double these prices for two cables, so 50 meters * 2 == $330 for the cable, not including connectors on both ends. Looks like we might be talking $500 for the cables. Ouch. Nonetheless, I'll have to factor that in against everything else. The transmitter chip and receiver chip seem to cost $32 in lowish quantities (~25), so that's another $128 per camera (two transmitters and two receivers). Add to the $500 estimate for cables and we're up to $628 (very roughly). Each of the CoaXPress chips (ECQO62R20 receiver and ECQO62T20 transmitter) is designed to receive or transmit one 6.25GHz differential signal at CML levels. Presumably you intend the 6.25GHz differential output of the ECQO62R20 receiver IC to flow into 2 pins of one cycloneV GT receiver (or transceiver), which presumably means those cycloneV GT recievers and transmitters can input and output 6.25GHz+ differential signals at CML levels. The datasheet talks about 8b/10b encoding NRZ encoded data and says the bitrate limit is 6.25Gbps, so I guess that means "no DDR tricks to effectively get 12.5Gbps". :-) The chips are small and appear quite convenient to apply, and I assume 8b/10b is trivial to implement in the FPGA. I suppose the chips wouldn't know better if the FPGA implemented something like 128b/130b instead to squeeze more data through. WOOPS. As I read the spec sheet, I assume the actual DATA throughput is 80% of 6.25Gbps == 5.00Gbps given the 8b/10b encoding. So I guess two of these cables will not be sending any more actual data than one 10Ge cable. Oh well, that's tolerable. I still don't have a good price on the 10Ge PHY chips, but one vague hint indicates they might cost twice as much as these CoaXPress chips. I definitely need better information on PHY prices. The cycloneV GT series FPGAs appear to cost roughly $200, $350, $500 for the three sizes. That's a lot cheaper than some of the altera FPGAs I was looking at for this project, but lots more than the $14 cyclone3 FPGA in my 1Ge camera. However, if these prices are 3x to 10x more than we'd actually have to pay in modest volume (100s or 1,000s and possibly 10,000s), then we're in the ballpark for this project. Depending on image sensor, we may need a lot of GPIO. Some of the cheap Aptina sensors have a very modest number of data-out signals, but some of the better and faster sensors output all 8,10,12,16 bits per pixel for several pixels at a time (up to 64 currently). That's a boatload of input signals! On the positive side, the wider the interface, the slower the bitrate at the FPGA GPIO pins, and thus the FPGA should be able to support the data rate easily. The Aptina sensors have a funky serial interface... maybe someone already developed IP for that interface. Obviously the key question for the cycloneV GT is whether they can handle 6.25Gbps at CML levels. A quick look at the overview indicates they may support 6.144Gbps transceivers, but doesn't say whether that's DDR or CML. I'll have to read a bit further to figure that out, I guess. Obviously it isn't a killer to slow down the interface from 6.25Gbps to 6.144Gbps if that's all there is to it. I see the overview says the cycloneV GX chips support 3.125Gbps. My crappy memory says 3.125Gbps is precisely what is required for the XAUI interface to some 10Ge PHYs (an alternative to the wide-parallel XGMII interface which requires much slower 312.5Mbps via DDR (so sorta 158MHz in a manner of speaking). The cycloneV GX FPGAs are somewhat cheaper than cycloneV GT, but not as much as I expected. Actually, the cycloneV E FPGAs aren't much cheaper either! Hmmm. I'll have to create a price matrix for all three series to understand what's happening here. Something doesn't make sense. I had assumed a 10Ge PHY with XGMII interface would be the best choice, because the FPGA would be lots cheaper (because XGMII doesn't require fast receivers or transmitters or anything else... pretty much just a plain old FPGA capable of 160MHz/320Mbps DDR on GPIO). But maybe that's not true. Maybe the cycloneV GX that hopefully/probably handles the 3.125Gbps XAUI interface is just as cheap, or nearly as cheap. It does seem much easier to find 10Ge PHYs with XAUI interfaces. Not sure they're any cheaper, though. Please correct any mistakes I made above, and expand on anything I said. Thanks for the idea. It might end up being a winner. Not sure yet.
