Altera_Forum
Honored Contributor
8 years agoFPGA2HPS SDRAM Bridge Appears to Be Working but data is Zeros
I'm using Q 17.1 I have tried this on numerous Evaluation boards -- but will describe it for the Macnica Sodia.
This same code scheme worked with the Helio Evaluation board which used an older GSRD as the starting point a few years back. I start with the Golden Design Quartus project AND the SD Card image. I add a custom IP where the firmware is responsible for writing data to SD RAM memory (On signal tap we can see that the data is getting written to the specified location). I create new *.rbf and new *.dtb to link the custom Linux device driver properly. I also create a new preloader and u-boot - but this doesn't make any difference it I use the original GOLDEN u-boot and preloader or the ones created for this specific project. The custom Linux device driver for this IP kmallocs two buffers and uses this address to set up the firmware IP. It then creates virtual addresses for user space for the "copy_to_user" in the read function. Linux indicates -- ALL THE BRIDGES ARE ENABLED and I actually have the FPGA configured from the EPCQ and can see from the LEDs that it is configured BEFORE u-boot starts. SIGNAL TAP indicates that the data is being moved by the firmware. BUT - when the device driver does the "copy_to_user" from the virtualAddress the user space code buffer is ALL ZEROS. ANY ADVISE WOULD BE GREATLY APPRECIATED !!!